/*********************************************************************************************************                                               
*                                     MCU ACH118X driver library
*                             COPYRIGHT(c) 2019 Amped RF Technology (ART)
*                                        All Rights Reserved
*
* File    : ach118x_syscfg.h
* Version : V1.0.0
* Brief   :
*  - Data structures and the address mapping for SYSCFG
*  - SYSCFG registers declarations and bits definition
*  - Macros to access SYSCFG register hardware
**********************************************************************************************************/

#ifndef __ACH118X_SYSCFG_H
#define __ACH118X_SYSCFG_H

//------------------------------------------------------------------------------------
//           SYSCFG Register Memory Map
//------------------------------------------------------------------------------------
#define SYSCFG_RST_REG                         0x00    //
#define SYSCFG_CFG_REG0                        0x04    //
#define SYSCFG_EXT_CLK_DIV_REG                 0x08    //
#define SYSCFG_CLK_CTRL_REG0                   0x0C    //
#define SYSCFG_CLK_CTRL_REG1                   0x10    //
#define SYSCFG_CODEC_SCAN_INP_REG0             0x14    //
#define SYSCFG_CODEC_SCAN_INP_REG1             0x18    //
#define SYSCFG_MEM_TEST_SECTOR0_REG0           0x1C    //
#define SYSCFG_MEM_TEST_SECTOR0_REG1           0x20    //
#define SYSCFG_MEM_TEST_SECTOR0_REG2           0x24    //
#define SYSCFG_MEM_TEST_SECTOR1_REG0           0x28    //
#define SYSCFG_MEM_TEST_SECTOR1_REG1           0x2C    //
#define SYSCFG_MEM_TEST_SECTOR1_REG2           0x30    //
#define SYSCFG_MEM_TEST_SECTOR2_REG0           0x34    //
#define SYSCFG_MEM_TEST_SECTOR2_REG1           0x38    //
#define SYSCFG_MEM_TEST_SECTOR2_REG2           0x3C    //
#define SYSCFG_MPU_COUNTER_REG                 0x40    //
#define SYSCFG_INTR_POLARITY_REG               0x44    //
#define SYSCFG_SYS_LEV_INTR_MASK_REG           0x48    //
#define SYSCFG_PLL0_REG0                       0x4C    //
#define SYSCFG_PLL0_REG1                       0x50    //
#define SYSCFG_Reserved_54                     0x54    //
#define SYSCFG_PLL1_REG0                       0x58    //
#define SYSCFG_PLL1_REG1                       0x5C    //
#define SYSCFG_SPREAD_SPECTRUM_PLL1_REG        0x60    //
#define SYSCFG_Reserved_64                     0x64    //
#define SYSCFG_PERIPHERAL_RST_ENB_REG          0x68    //
#define SYSCFG_PAD_ENB_REG0                    0x6C    //
#define SYSCFG_PAD_ENB_REG1                    0x70    //
#define SYSCFG_CLK_STATUS_REG                  0x84    //
#define SYSCFG_INTR_STATUS_REG                 0x88    //
#define SYSCFG_PLL1_SPREAD_SPECTRUM_REG        0x8C    //
#define SYSCFG_STATUS_REG0                     0x90    //
#define SYSCFG_STATUS_REG1                     0x94    //
#define SYSCFG_Reserved_94                     0x98    //
#define SYSCFG_STATUS_REG2                     0x9C    //
#define SYSCFG_CLK_ENB_REG                     0xA0    //
#define SYSCFG_Reserved_A4                     0xA4    //
#define SYSCFG_CODEC_SCAN_OUT_REG0             0xA8    //
#define SYSCFG_CODEC_SCAN_OUT_REG1             0xAC    //


typedef struct
{
    vu32 RESET_REG;                     // 0x00
    vu32 CFG_REG0;                      // 0x04
    vu32 EXT_CLK_DIV_REG;               // 0x08
    vu32 CLK_CTRL_REG0;                 // 0x0C
    vu32 CLK_CTRL_REG1;                 // 0x10
    vu32 CODEC_SCAN_INP_REG0;           // 0x14
    vu32 CODEC_SCAN_INP_REG1;           // 0x18
    vu32 MEM_TEST_SECTOR0_REG0;         // 0x1C
    vu32 MEM_TEST_SECTOR0_REG1;         // 0x20
    vu32 MEM_TEST_SECTOR0_REG2;         // 0x24
    vu32 MEM_TEST_SECTOR1_REG0;         // 0x28
    vu32 MEM_TEST_SECTOR1_REG1;         // 0x2C
    vu32 MEM_TEST_SECTOR1_REG2;         // 0x30
    vu32 MEM_TEST_SECTOR2_REG0;         // 0x34
    vu32 MEM_TEST_SECTOR2_REG1;         // 0x38
    vu32 MEM_TEST_SECTOR2_REG2;         // 0x3C
    vu32 MPU_COUNTER_REG;               // 0x40
    vu32 INTR_POLARITY_REG;             // 0x44
    vu32 SYS_LEV_INTR_MASK_REG;         // 0x48
    vu32 PLL0_REG0;                     // 0x4C
    vu32 PLL0_REG1;                     // 0x50
    vu32 Reserved_54;                   // 0x54
    vu32 PLL1_REG0;                     // 0x58
    vu32 PLL1_REG1;                     // 0x5C
    vu32 SPREAD_SPECTRUM_PLL1_REG;      // 0x60
    vu32 Reserved_64;                   // 0x64
    vu32 PERIPHERAL_RESET_ENB_REG;      // 0x68
    vu32 PAD_ENB_REG0;                  // 0x6C
    vu32 PAD_ENB_REG1;                  // 0x70
    vu32 CLK_STATUS_REG;                // 0x84
    vu32 INTR_STATUS_REG;               // 0x88
    vu32 PLL1_SPREAD_SPECTRUM_REG;      // 0x8C
    vu32 STATUS_REG0;                   // 0x90
    vu32 STATUS_REG1;                   // 0x94
    vu32 Reserved_94;                   // 0x98
    vu32 STATUS_REG2;                   // 0x9C
    vu32 CLK_ENB_REG;                   // 0xA0
    vu32 Reserved_A4;                   // 0xA4
    vu32 CODEC_SCAN_OUT_REG0;           // 0xA8
    vu32 CODEC_SCAN_OUT_REG1;           // 0xAC
} SysCfg_Typedef;


//------------------------------------------------------------------------------------
// Interrupt Mask bits
//------------------------------------------------------------------------------------
#define SPI0_IRQ_MASK       0x00000001          // b0   SPI0 Interrupt mask
#define SPI1_IRQ_MASK       0x00000002          // b1   SPI1 Interrupt mask
#define SPI2_IRQ_MASK       0x00000004          // b2   SPI2 Interrupt mask
#define I2S0_IRQ_MASK       0x00000008          // b3   I2S0 mask
#define Uart0_IRQ_MASK      0x00000010          // b4   Uart0 Interrupt mask
#define Uart1_IRQ_MASK      0x00000020          // b5   Uart1 Interrupt mask
#define Uart2_IRQ_MASK      0x00000040          // b6   Uart2 Interrupt mask
#define I2S1_IRQ_MASK       0x00000080          // b7   I2S1 Interrupt mask
#define I2C0_IRQ_MASK       0x00000100          // b8   I2C0 Interrupt mask
#define TIM_IRQ_MASK        0x00000200          // b9   Timer Interrupt mask
#define GPIO3_IRQ_MASK      0x00000400          // b10  GPIO3 Interrupt mask
#define WDOG_IRQ_MASK       0x00000800          // b11  WDOG timer Interrupt mask
#define ADC0_IRQ_MASK       0x00001000          // b12  ADC0 Interrupt mask
#define ADC1_IRQ_MASK       0x00002000          // b13  ADC1 Interrupt mask
#define AES_IRQ_MASK        0x00004000          // b14  AES Interrupt mask
#define DMAC_IRQ_MASK       0x00020000          // b17  DMAC Interrupt mask
#define GPIO2_00_IRQ_MASK   0x00040000          // b18  GPIO2 b1 Interrupt mask
#define GPIO2_01_IRQ_MASK   0x00080000          // b19  GPIO2 b2 Interrupt mask
#define GPIO2_02_IRQ_MASK   0x00100000          // b20  GPIO2 b3 Interrupt mask
#define GPIO2_03_IRQ_MASK   0x00200000          // b21  GPIO2 b4 Interrupt mask
#define GPIO2_04_IRQ_MASK   0x00400000          // b22  GPIO2 b5 Interrupt mask
#define GPIO2_05_IRQ_MASK   0x00800000          // b23  GPIO2 b6 Interrupt mask
#define GPIO2_06_IRQ_MASK   0x01000000          // b24  GPIO2 b7 Interrupt mask
#define GPIO2_07_IRQ_MASK   0x02000000          // b25  GPIO2 b8 Interrupt mask
#define GPIO2_08_IRQ_MASK   0x04000000          // b26  GPIO2 b9 Interrupt mask
#define GPIO2_09_IRQ_MASK   0x08000000          // b27  GPIO2 b10 Interrupt mask
#define GPIO2_10_IRQ_MASK   0x10000000          // b28  GPIO2 b11 Interrupt mask
#define GPIO2_11_IRQ_MASK   0x20000000          // b29  GPIO2 b12 Interrupt mask
#define GPIO2_12_IRQ_MASK   0x40000000          // b30  GPIO2 b13 Interrupt mask


//------------------------------------------------------------------------------------
//    SysCfg & PMU Register Definitions  (0x4003 5800 - 0x4003 5FFF)
//------------------------------------------------------------------------------------

#define SYS_CFG_RST_REG_BASE       (SYSCFG_REG_BASE | SYSCFG_RST_REG)
typedef struct {
    uint32_t                    // Defaults:
        SSI_RST0_N      : 1,    // 0
        SSI_RST1_N      : 1,    // 0
        SSI_RST2_N      : 1,    // 0
        SSI2S0_SRESETN  : 1,    // 0
        I2S1_CH4_SRESETN: 1,    // 0
        IC_I2C_RST_N    : 1,    // 0
        TIMER_1_RESETN  : 1,    // 0
        RSTB            : 1,    // 0
        SHRESETN        : 1,    // 0
        MHRESETN        : 1,    // 0
        S0_DUT_PRESETN  : 1,    // 0
        S1_DUT_PRESETN  : 1,    // 0
        SYS_CFG_RSTN    : 1,    // 0
        SYSTEM_RESET    : 1,    // 0
        SPEED_UP_WDT_SYS_CFG: 1,// 0
        SECONDARY_WD_ENB: 1;    // 0
} SYS_CFG_RST_REG_Typedef;
#define SYS_CFG_RST_REG  ((volatile SYS_CFG_RST_REG_Typedef *) SYS_CFG_RST_REG_BASE)

//============================================================================

#define CLK_CNTRL_REG0_BASE       (SYSCFG_REG_BASE | SYSCFG_CLK_CTRL_REG0)
typedef struct {
    uint32_t                    // Defaults:
        Reserved_0_3    : 4,    //
        HCLK_sel        : 1,    // 0
        Reserved_5_31   : 27;
} CLK_CNTRL_REG0_Typedef;
#define CLK_CNTRL_REG0  ((volatile CLK_CNTRL_REG0_Typedef *) CLK_CNTRL_REG0_BASE)

//============================================================================

#define CLK_CNTRL_REG1_BASE       (SYSCFG_REG_BASE | SYSCFG_CLK_CTRL_REG1)
typedef struct {
    uint32_t                        // Defaults:
        IO_SS_IN_N          : 1,    // 1
        IO_SS_IN_1          : 1,    // 1
        IO_SS_IN_2          : 1,    // 1

        IO_DSR_N_0          : 1,    // 0
        IO_DCD_N_0          : 1,    // 1
        IO_RI_N_0           : 1,    // 1

        IO_DSR_N_1          : 1,    // 0
        IO_DCD_N_1          : 1,    // 1
        IO_RI_N_1           : 1,    // 1

        IO_DSR_N_2          : 1,    // 0
        IO_DCD_N_2          : 1,    // 1
        IO_RI_N_2           : 1,    // 1

        SPEED_UP_WDT_ADC1   : 1,    // 0
        SPEED_UP_WDT_ADC2   : 1,    // 0
        SPEED_UP_WDT_AES    : 1,    // 0
        Reserved_15_17      : 3,    //
        INTFSEL             : 1,    // 1

        I2S1_CLK_STG1_SEL   : 1,    // 0 -- 1 = DIV4
        Reserved_20         : 1,    //

        CODEC_CLK_SEL       : 1,    // 0 - Selection for CODEC clk
        I2S1_CLK_SEL        : 1,    // 0
        CODEC_WORD_SEL      : 1,    // 0
        CODEC_DATA_INPUT    : 1,    // 0
        I2S0_CLK_SEL        : 1,    // 0
        I2S0_CLK_STG1_SEL   : 1,    // 0 - Muxed internal signal

        Reserved_27_31      : 5;
} CLK_CNTRL_REG1_Typedef;
#define CLK_CNTRL_REG1  ((volatile CLK_CNTRL_REG1_Typedef *) CLK_CNTRL_REG1_BASE)

//============================================================================
#define PLL0_REG0_BASE        (SYSCFG_REG_BASE | SYSCFG_PLL0_REG0)  // Main
#define PLL1_REG0_BASE        (SYSCFG_REG_BASE | SYSCFG_PLL1_REG0)  // Audio
typedef struct {
    uint32_t                    // Defaults:
        REFDIV          : 6,    // 1
        FBDIV           : 12,   // 23
        POSTDIV1        : 3,    // 3
        POSTDIV2        : 3,    // 2
        DIVVAL          : 4,
        Reserved_24_31  : 1;
} PLL_REG0_Typedef;
#define PLL0_REG0   ((volatile PLL_REG0_Typedef *)  PLL0_REG0_BASE)
#define PLL1_REG0   ((volatile PLL_REG0_Typedef *)  PLL1_REG0_BASE)

//============================================================================
#define PLL0_REG1_BASE       (SYSCFG_REG_BASE | SYSCFG_PLL0_REG1)   // Main
#define PLL1_REG1_BASE       (SYSCFG_REG_BASE | SYSCFG_PLL1_REG1)   // Audio
typedef struct {
    uint32_t                    // Defaults:
        FRAC            : 24,   // 2653381
        PD              : 1,    // 1
        DACPD           : 1,    // 0
        DSMPD           : 1,    // 0
        FOUTPOSTDIVPD   : 1,    // 0
        FOUT4PHASEPD    : 1,    // 0
        FOUTVCOPD       : 1,    // 0
        BYPASS          : 1,    // 0
        Reserved_31     : 1;
} PLL_REG1_Typedef;
#define PLL0_REG1  ((volatile PLL_REG1_Typedef *) PLL0_REG1_BASE)
#define PLL1_REG1  ((volatile PLL_REG1_Typedef *) PLL1_REG1_BASE)

//============================================================================

#define OUTPUT_ENABLE_REG0_BASE       (SYSCFG_REG_BASE | SYSCFG_PAD_ENB_REG0)
typedef struct {
    uint32_t                    // Defaults:
        P01             : 2,    // 0
        P02             : 2,    // 0
        P03             : 2,    // 0
        P04             : 2,    // 0
        Reserved_8_15   : 8,
        P09             : 2,    // 0
        P10             : 2,    // 0
        P11             : 2,    // 0
        P12             : 2,    // 0
        P13             : 2,    // 0
        P14             : 2,    // 0
        P15             : 2,    // 0
        P16             : 2;    // 0
} OUTPUT_ENABLE_REG0_Typedef;
#define OUTPUT_ENABLE_REG0  ((volatile OUTPUT_ENABLE_REG0_Typedef *) OUTPUT_ENABLE_REG0_BASE)

//============================================================================

#define OUTPUT_ENABLE_REG1_BASE       (SYSCFG_REG_BASE | SYSCFG_PAD_ENB_REG1)
typedef struct {
    uint32_t                    // Defaults:
        P17             : 2,    // 0
        Reserved_2_13   : 12,
        P24             : 2,
        P25             : 2,
        P26             : 2,
        P27             : 2,
        Reserved_22_31  : 10;
} OUTPUT_ENABLE_REG1_Typedef;
#define OUTPUT_ENABLE_REG1  ((volatile OUTPUT_ENABLE_REG1_Typedef *) OUTPUT_ENABLE_REG1_BASE)

//============================================================================

#define CLK_STATUS_REG_BASE       (SYSCFG_REG_BASE | SYSCFG_CLK_STATUS_REG)
typedef struct {
    uint32_t
        BOOT            : 1,
        MAIN_PLL        : 1,
        AUDIO_PLL       : 1,
        Reserved_3_31   : 29;
} CLK_STATUS_REG_Typedef;
#define CLK_STATUS  ((volatile CLK_STATUS_REG_Typedef *) CLK_STATUS_REG_BASE)


#endif /* __ACH118X_SYSCFG_H */
/************************ (C) COPYRIGHT ART *****END OF FILE****/
