/******************************************************************************
* ach118x_ssi.h
* 21-June-2017
* This file contains:
*  - Data structures and the address mapping for SSI
*  - SSI registers declarations and bits definition
*  - Macros to access SSI register hardware
*
* COPYRIGHT(c) 2017 Amped RF Technology (ART) -- All rights reserved.
******************************************************************************/
#ifndef __ACH118X_SSI_H
#define __ACH118X_SSI_H

/*************************************************************************/
/*                 SSI (SPI) Definitions                                 */
/*************************************************************************/
#define SSI_CTRLR0                  0x00    // Control Register 0
#define SSI_CTRLR1                  0x04    // Control Register 1
#define SSI_SSIENR                  0x08    // SSI Enable Register
#define SSI_MWCR                    0x0C    // Microwire Control Register
#define SSI_SER                     0x10    // Slave Enable Register
#define SSI_BAUDR                   0x14    // Baud Rate Select
#define SSI_TXFTLR                  0x18    // Transmit FIFO Threshold Level
#define SSI_RXFTLR                  0x1C    // Receive FIFO Threshold Level
#define SSI_TXFLR                   0x20    // Transmit FIFO Level Register
#define SSI_RXFLR                   0x24    // Receive FIFO Level Register
#define SSI_SR                      0x28    // Status Register
#define SSI_IMR                     0x2C    // Interrupt Mask Register
#define SSI_ISR                     0x30    // Interrupt Status Register
#define SSI_RISR                    0x34    // Raw Interrupt Status Register
#define SSI_TXOICR                  0x38    // Transmit FIFO Overflow Interrupt Clear Register
#define SSI_RXOCR                   0x3C    // Receive FIFO Overflow Interrupt Clear Register
#define SSI_RXUICR                  0x40    // Receive FIFO Underflow Interrupt Clear Register
#define SSI_MSTICR                  0x44    // Multi-Master Interrupt Clear Register
#define SSI_ICR                     0x48    // Interrupt Clear Register
#define SSI_DMACTRLR                0x4C    // DMA Control Register
#define SSI_DMATDLR                 0x50    // DMA Transmit Data Level
#define SSI_DMARDLR                 0x54    // DMA Receive Data Level
#define SSI_IDR                     0x58    // Identification Register
#define SSI_SSI_COMP_VERSION        0x5C    // coreKit version ID register
#define SSI_DR                      0x60    // Data Register
#define SSI_RX_SAMPLE_DLY           0xF0    // RXD Sample Delay Register
#define SSI_SPI_CTRLR0              0xF4    // SPI control register
#define SSI_RSVD_1                  0xF8    // Reserved location for future use
#define SSI_RSVD_2                  0xFC    // Reserved location for future use


#define SPI_FIFO_DEPTH              (22)    // SPI FIFO Depth

/**
  * @brief  SPI Init structure definition
  */
typedef struct
{
    u16 TRANS_TYPE;
    u16 ADDR_L;
    u16 INST_L;
    u16 WAIT_CYCLES;
    //-------------------
	u16 SPI_FRF;
	u16 DFS_32;
	u16 CFS;
	u16 SRL;
	u16 SLV_OE;
	u16 TMOD;
	u16 SCPOL;
	u16 SCPH;
	u16 FRF;
	u16 DFS;
    //-------------------
	u16 NumOfDataFrame;
	u16 ClockDivider;
	u16 TX_FIFO_ThresholdLevel;
	u16 RX_FIFO_ThresholdLevel;
	u32 SlaveSlect;
}SPI_InitTypeDef;

/*------------------------ Serial Peripheral Interface -----------------------*/
/*SPI register define*/

typedef struct {
    vu32
        DFS                 : 4,
        FRF                 : 2,
        SCPH                : 1,
        SCPOL               : 1,
        TMOD                : 2,
        SLV_OE              : 1,
        SRL                 : 1,
        CFS                 : 4,
        DFS_32              : 5,
        SPI_FRF             : 2,
        Reserved_31_23      : 9;
} SSI_CTRLR0_Typedef;

typedef struct {
    vu32
        TRANS_TYPE          : 2,
        ADDR_L              : 4,
        Reserved_7_6        : 2,
        INST_L              : 2,
        Reserved_10         : 1,
        WAIT_CYCLES         : 4,
        Reserved_31_15      : 17;
} SPI_CTRLR0_Typedef;

#define SSI_BUFFER_LEN		36
typedef struct
{
	SSI_CTRLR0_Typedef CTRLR0;	    /*0x00, Control Register 0*/
	vu32 CTRLR1;				    /*0x04, Control Register 1*/
	vu32 SSIENR;				    /*0x08, SSI Enable register*/
	vu32 MWCR;					    /*0x0c, Microwire Control Register*/
	vu32 SER;					    /*0x10, Slave Enable Register*/
	vu32 BAUDR;					    /*0x14, Baud Rate Select*/
	vu32 TXFTLR;				    /*0x18, Transmit FIFO Threshold Level */
	vu32 RXFTLR;				    /*0x1c, Receive FIFO Threshold Level*/
	vu32 TXFLR;					    /*0x20, Transmit FIFO Level Register */
	vu32 RXFLR;					    /*0x24, Receive FIFO Level Register*/
	vu32 SR;					    /*0x28, Status Register*/
	vu32 IMR;					    /*0x2c, Interrupt Mask Register */
	vu32 ISR;					    /*0x30, Interrupt Status Register */
	vu32 RISR;					    /*0x34, Raw Interrupt Status Register */
	vu32 TXOICR;				    /*0x38, Transmit FIFO Overflow Interrupt Clear Register */
	vu32 RXOICR;				    /*0x3c, Receive FIFO Overflow Interrupt Clear Register */
	vu32 RXUICR;				    /*0x40, Receive FIFO Underflow Interrupt Clear Register */
	vu32 MSTICR;				    /*0x44, Multi-Master Interrupt Clear Register*/
	vu32 ICR;					    /*0x48, Interrupt Clear Register*/
	vu32 DMACR;					    /*0x4c, DMA Control Register*/
	vu32 DMATDLR;				    /*0x50, DMA Transmit Data Level register*/
	vu32 DMARDLR;				    /*0x54, DMA Receive Data Level register*/
	vu32 IDR;					    /*0x58, Identification Register*/
	vu32 SSI_COMP_VERSION;		    /*0x5c, coreKit version ID register*/
	vu32 DR[SSI_BUFFER_LEN];	    /*0x60-0xec, Data Register*/
	vu32 RX_SAMPLE_DLY;			    /*0xf0, RXD Sample Delay Register*/
	SPI_CTRLR0_Typedef SPI_CTRLR0;	/*0xf4, SPI control register*/
	vu32 RSVD_1;				    /*0xf8, Reserved*/
	vu32 RSVD_2;				    /*0xfc, Reserved*/
}SPI_Typedef;

/**********Register and Field Description for SPI************/

/**CTRLR0 Bit**/
#define CTRLR0_DQ_WAIR_BIT_SHIFT		(28)
#define CTRLR0_DQ_WAIR_BIT_MASK			(0xf << CTRLR0_DQ_WAIR_BIT_SHIFT)
typedef enum
{
	Wait_0_Cycles = 0,
	Wait_1_Cycle,
	Wait_2_Cycles,
	Wait_3_Cycles,
	Wait_4_Cycles,
	Wait_5_Cycles,
	Wait_6_Cycles,
	Wait_7_Cycles,
	Wait_8_Cycles,
	Wait_9_Cycles,
	Wait_10_Cycles,
	Wait_11_Cycles,
	Wait_12_Cycles,
	Wait_13_Cycles,
	Wait_14_Cycles,
	Wait_15_Cycles
}DQ_WAIT_CYCLES;

#define CTRLR0_DQ_INST_BIT_SHIFT		(26)
#define CTRLR0_DQ_INST_BIT_MASK			(0x3 << CTRLR0_DQ_INST_BIT_SHIFT)
typedef enum
{
	Inst_len_0_bit = 0,
	Inst_len_4_bits,
	Inst_len_8_bits,
	Inst_len_12_bits,
}DQ_INST_LEN;

#define CTRLR0_SPI_TRANS_BIT_SHIFT		(24)
#define CTRLR0_SPI_TRANS_BIT_MASK		(0x3 << CTRLR0_SPI_TRANS_BIT_SHIFT)
typedef enum
{
	TRANS_Standard_Mode = 0,
	TRANS_Mixed_Mode,
	TRANS_FRF_Mode,
	TRANS_Resvered_Mode,
}SPI_TRANS_MODE;


#define CTRLR0_SPI_FRF_BIT_SHIFT		(21)
#define CTRLR0_SPI_FRF_BIT_MASK			(0x3 << CTRLR0_SPI_FRF_BIT_SHIFT)
typedef enum
{
	SPI_FRF_Standard = 0,
	SPI_FRF_Dual,
	SPI_FRF_Quad,
}SPI_FRF;

#define CTRLR0_DFS_32_BIT_SHIFT			(16)
#define CTRLR0_DFS_32_BIT_MASK			(0x1f << CTRLR0_DFS_32_BIT_SHIFT)
typedef enum
{
	DF32_4_bit = 0x3,
	DF32_5_bit,
	DF32_6_bit,
	DF32_7_bit,
	DF32_8_bit,
	DF32_9_bit,
	DF32_10_bit,
	DF32_11_bit,
	DF32_12_bit,
	DF32_13_bit,
	DF32_14_bit,
	DF32_15_bit,
	DF32_16_bit,
	DF32_17_bit,
	DF32_18_bit,
	DF32_19_bit,
	DF32_20_bit,
	DF32_21_bit,
	DF32_22_bit,
	DF32_23_bit,
	DF32_24_bit,
	DF32_25_bit,
	DF32_26_bit,
	DF32_27_bit,
	DF32_28_bit,
	DF32_29_bit,
	DF32_30_bit,
	DF32_31_bit,
	DF32_32_bit,
}SPI_DFS32;

#define CTRLR0_CFS_BIT_SHIFT			(12)
#define CTRLR0_CFS_BIT_MASK				(0xf << CTRLR0_CFS_BIT_SHIFT)
typedef enum
{
	CFS_Address_0_bit = 0,
	CFS_Address_4_bit,
	CFS_Address_8_bit,
	CFS_Address_12_bit,
	CFS_Address_16_bit,
	CFS_Address_24_bit,
	CFS_Address_28_bit,
	CFS_Address_32_bit,
	CFS_Address_36_bit,
	CFS_Address_40_bit,
	CFS_Address_44_bit,
	CFS_Address_48_bit,
	CFS_Address_52_bit,
	CFS_Address_56_bit,
	CFS_Address_60_bit
}SPI_CFS_ADDRESS_WIDTH;

typedef enum
{
	DFS_Control_1_bit=0,
	DFS_Control_2_bit,
	DFS_Control_3_bit,
	DFS_Control_4_bit,
	DFS_Control_5_bit,
	DFS_Control_6_bit,
	DFS_Control_7_bit,
	DFS_Control_8_bit,
	DFS_Control_9_bit,
	DFS_Control_10_bit,
	DFS_Control_11_bit,
	DFS_Control_12_bit,
	DFS_Control_13_bit,
	DFS_Control_14_bit,
	DFS_Control_15_bit,
	DFS_Control_16_bit
}SPI_DFS32_CTRL_WORD;

#define CTRLR0_SRL_BIT_SHIFT			(11)
#define CTRLR0_SRL_BIT_MASK				(0x1 << CTRLR0_SRL_BIT_SHIFT)
#define SRL_NORMAL_Mode					(0)
#define SRL_Test_Mode					(1)

#define CTRLR0_SLV_OE_BIT_SHIFT			(10)
#define CTRLR0_SLV_OE_BIT_MASK			(0x1 << CTRLR0_SLV_OE_BIT_SHIFT)
#define SLAVE_TXD_Enable				(0)
#define SLAVE_TXD_Disable				(1)

#define CTRLR0_TMOD_BIT_SHIFT			(8)
#define CTRLR0_TMOD_BIT_MASK			(0x3 << CTRLR0_TMOD_BIT_SHIFT)
typedef enum
{
	Mode_Tx_and_Rx = 0,
	Mode_Tx_only,
	Mode_Rx_only,
	Mode_E2PROM_read
}SPI_TXRX_MODE;

#define CTRLR0_SCPOL_BIT_SHIFT			(7)
#define CTRLR0_SCPOL_BIT_MASK			(0x1 << CTRLR0_SCPOL_BIT_SHIFT)
typedef enum
{
	SCPOL_low = 0,
	SCPOL_high,
}SPI_SCPOL;

#define CTRLR0_SCPH_BIT_SHIFT			(6)
#define CTRLR0_SCPH_BIT_MASK			(0x1 << CTRLR0_SCPH_BIT_SHIFT)
typedef enum
{
	SCPH_middle_1st = 0,
	SCPH_start_1st,
}SPI_SCPH;

#define CTRLR0_FRF_BIT_SHIFT			(4)
#define CTRLR0_FRF_BIT_MASK				(0x3 << CTRLR0_FRF_BIT_SHIFT)
typedef enum
{
	FRF_Motorola = 0,
	FRF_Texas,
	FRF_Microwire,
	FRF_Reserved
}FRF;


#define CTRLR0_DFS_BIT_SHIFT			(0)
#define CTRLR0_DFS_BIT_MASK				(0xf << CTRLR0_DFS_BIT_SHIFT)
typedef enum
{
	DFS16_4_bit=0x3,
	DFS16_5_bit,
	DFS16_6_bit,
	DFS16_7_bit,
	DFS16_8_bit,
	DFS16_9_bit,
	DFS16_10_bit,
	DFS16_11_bit,
	DFS16_12_bit,
	DFS16_13_bit,
	DFS16_14_bit,
	DFS16_15_bit,
	DFS16_16_bit
}SPI_DFS;

/**CTRLR1 Bit**/
#define CTRLR1_NDF_BIT_SHIFT		(0)
#define CTRLR1_NDF_BIT_MASK			(0xff << CTRLR1_NDF_BIT_SHIFT)

/**SSIENR Bit**/
#define CTRLR1_ENABLE_BIT_SHIFT		(0)
#define SSIENR_ENABLE_BIT_MASK		(1 << CTRLR1_ENABLE_BIT_SHIFT)
#define SSI_ENABLE	(0)
#define SSI_DISABLE	(1)

/**MWCR Bit**/
#define MWCR_MHS_BIT_SHIFT			(2)
#define MWCR_MHS_BIT_MASK			(1 << MWCR_MHS_BIT_SHIFT)
#define MHS_Disable					(0)
#define MHS_Enable					(1)

#define MWCR_MOD_BIT_SHIFT			(1)
#define MWCR_MOD_BIT_MASK			(1 << MWCR_MOD_BIT_SHIFT)
#define MOD_receieve				(0)
#define MOD_transmit				(1)

#define MWCR_MWMOD_BIT_SHIFT		(0)
#define MWCR_MWMOD_BIT_MASK			(1 << MWCR_MWMOD_BIT_SHIFT)
#define MWMOD_non_sequential		(0)
#define MWMOD_sequential			(1)

/**SER Bit**/
#define SSI_NUM_SLAVES				(1)//This dues to IP hardware
#define SSI_NUM_SLAVES_BIT_SHIFT	(0)
#define SSI_NUM_SLAVES_BIT_MASK		(SSI_NUM_SLAVES << SSI_NUM_SLAVES_BIT_SHIFT)
#define SLAVE_Not_selected			(0)
#define SLAVE_selected				(1)

/**BAUDR Bit**/
#define BAUDR_SCKDV_BIT_SHIFT		(0)
#define BAUDR_SCKDV_BIT_MASK		(0xff << BAUDR_SCKDV_BIT_SHIFT)

/**TXFTLR Bit**/
//#define TX_ABW					(7)
#define TXFTLR_TFT_BIT_SHIFT		(0)
#define TXFTLR_TFT_BIT_MASK			(0xff << TXFTLR_TFT_BIT_SHIFT)

/**TXFTLR Bit**/
//#define TX_ABW					(7)
#define TXFTLR_TXTFL_BIT_SHIFT		(0)
#define TXFTLR_TXTFL_BIT_MASK		(0xff << TXFTLR_TXTFL_BIT_SHIFT)

/**RXFLR Bit**/
//#define RX_ABW					(7)
#define RXFLR_RXTFL_BIT_SHIFT		(0)
#define RXFLR_RXTFL_BIT_MASK		(0xff << RXFTLR_RTXTFL_BIT_SHIFT)

/**SR Bit**/
#define SSI_SR_BUSY     0x01    // SSI Busy Flag
#define SSI_SR_TFNF     0x02    // Transmit FIFO Not Full
#define SSI_SR_TFE      0x04    // Transmit FIFO Empty
#define SSI_SR_RFNE     0x08    // Receive FIFO Not Empty
#define SSI_SR_RFF      0x10    // Receive FIFO Full
#define SSI_SR_TXE      0x20    // Transmission Error
#define SSI_SR_DCOL     0x40    // Data Collision Error

#define SR_DCOL_BIT_SHIFT		(6)
#define SR_DCOL_BIT_MASK		(1 << SR_DCOL_BIT_SHIFT)
#define SR_DCOL_Flag			(1 << SR_DCOL_BIT_SHIFT)

#define SR_TXE_BIT_SHIFT		(5)
#define SR_TXE_BIT_MASK			(1 << SR_TXE_BIT_SHIFT)
#define SR_TXE_Flag				(1 << SR_TXE_BIT_SHIFT)

#define SR_RFF_BIT_SHIFT		(4)
#define SR_RFF_BIT_MASK			(1 << SR_RFF_BIT_SHIFT)
#define SR_RFF_Flag				(1 << SR_RFF_BIT_SHIFT)

#define SR_RFNE_BIT_SHIFT		(3)
#define SR_RFNE_BIT_MASK		(1 << SR_RFNE_BIT_SHIFT)
#define SR_RFNE_Flag			(1 << SR_RFNE_BIT_SHIFT)

#define SR_TFE_BIT_SHIFT		(2)
#define SR_TFE_BIT_MASK			(1 << SR_TFE_BIT_SHIFT)
#define SR_TFE_Flag				(1 << SR_TFE_BIT_SHIFT)

#define SR_TFNF_BIT_SHIFT		(1)
#define SR_TFNF_BIT_MASK		(1 << SR_TFNF_BIT_SHIFT)
#define SR_TFNF_Flag			(1 << SR_TFNF_BIT_SHIFT)

#define SR_BUSY_BIT_SHIFT		(0)
#define SR_BUSY_BIT_MASK		(1 << SR_TFNE_BIT_SHIFT)
#define SR_BUSY_Flag			(1 << SR_TFNE_BIT_SHIFT)

//For register IMR ISR RISR
#define SSI_IT_TXE      0x01    // Transmit FIFO Empty
#define SSI_IT_TXO      0x02    // Transmit FIFO Overflow
#define SSI_IT_RXU      0x04    // Receive FIFO Underflow
#define SSI_IT_RXO      0x08    // Receive FIFO Overflow
#define SSI_IT_RXF      0x10    // Receive FIFO Full
#define SSI_IT_MST      0x20    // Multi-Master Contention

#define IT_MST_BIT_SHIFT		(5)
#define IT_MASK_MST_Flag		(1 << IT_MST_BIT_SHIFT)
#define IT_RAW_MST_Flag			(1 << IT_MST_BIT_SHIFT)
#define IT_MST_Flag				(1 << IT_MST_BIT_SHIFT)

#define IT_RXF_BIT_SHIFT		(4)
#define IT_MASK_RXF_Flag		(1 << IT_RXF_BIT_SHIFT)
#define IT_RAW_RXF_Flag			(1 << IT_RXF_BIT_SHIFT)
#define IT_RXF_Flag				(1 << IT_RXF_BIT_SHIFT)

#define IT_RXO_BIT_SHIFT		(3)
#define IT_MASK_RXO_Flag		(1 << IT_RXO_BIT_SHIFT)
#define IT_RAW_RXO_Flag			(1 << IT_RXO_BIT_SHIFT)
#define IT_RXO_Flag				(1 << IT_RXO_BIT_SHIFT)

#define IT_RXU_BIT_SHIFT		(2)
#define IT_MASK_RXU_Flag		(1 << IT_RXU_BIT_SHIFT)
#define IT_RAW_RXU_Flag			(1 << IT_RXU_BIT_SHIFT)
#define IT_RXU_Flag				(1 << IT_RXU_BIT_SHIFT)

#define IT_TXO_BIT_SHIFT		(1)
#define IT_MASK_TXO_Flag		(1 << IT_TXO_BIT_SHIFT)
#define IT_RAW_TXO_Flag			(1 << IT_TXO_BIT_SHIFT)
#define IT_TXO_Flag				(1 << IT_TXO_BIT_SHIFT)

#define IT_TXE_BIT_SHIFT		(1)
#define IT_MASK_TXE_Flag		(1 << IT_TXE_BIT_SHIFT)
#define IT_RAW_TXE_Flag			(1 << IT_TXE_BIT_SHIFT)
#define IT_TXE_Flag				(1 << IT_TXE_BIT_SHIFT)





#if 0
typedef enum{
	Enable = 0,
	Disable
} FunctionalState;

typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#endif

/* Initialization and Configuration functions *********************************/
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void SPI_DeInit(SPI_Typedef* SPIx);
void SPI_Cmd(SPI_Typedef* SPIx, FunctionalState NewState);
void SPI_SetSlaveEbale(SPI_Typedef* SPIx, u8 SLAVE_NUM);
FlagStatus SPI_GetStatusFlag(SPI_Typedef* SPIx, u16 SPI_FLAG);
FlagStatus SPI_GetITMaskFlag(SPI_Typedef* SPIx, u8 SPI_Mask_IT);
void SPI_ITMaskConfig(SPI_Typedef* SPIx, u8 SPI_Mask_IT, FunctionalState NewState);
FlagStatus SPI_GetRawITFlag(SPI_Typedef* SPIx, u8 SPI_Mask_IT);
void SPI_RawITConfig(SPI_Typedef* SPIx, u8 SPI_Raw_IT, FunctionalState NewState);
FlagStatus SPI_ClearTxFifoOverflowIT(SPI_Typedef* SPIx);
FlagStatus SPI_ClearRxFifoOverflowIT(SPI_Typedef* SPIx);
FlagStatus SPI_ClearRxFifoUnderflowIT(SPI_Typedef* SPIx);
FlagStatus SPI_ClearMultimasterIT(SPI_Typedef* SPIx);
FlagStatus SPI_ClearITs(SPI_Typedef* SPIx);
void SPI_SendData(SPI_Typedef* SPIx, u8 Data);
void SPI_SendDataBuf(SPI_Typedef* SPIx, u8 *pData, u16 len);
u8 SPI_GetData(SPI_Typedef* SPIx, u8 *pData);
void SPI_GetDataBuf(SPI_Typedef* SPIx, u8 *pData, u16 len);
void SPI_SendAndGetData(SPI_Typedef* SPIx, u8 *pSndBuf, u32 SndLen, u8 *pRcvBuf, u32 RcvLen);
void SPI_SendAndGetDataShort(SPI_Typedef* SPIx, u8 *pSndBuf, u32 SndLen, u8 *pRcvBuf, u32 RcvLen);
void SPI_SendAndGetDataSlow(SPI_Typedef* SPIx, u8 *pSndBuf, u32 SndLen, u8 *pRcvBuf, u32 RcvLen);
int  SPI_SendAndGetDataIRQ(SPI_Typedef* SPIx, u8 *pSndBuf, u32 SndLen, u8 *pRcvBuf, u32 RcvLen);
void SPI_Init(SPI_Typedef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
uint32_t SPI_GetComponentID(SPI_Typedef* SPIx);
uint32_t SPI_GetComponentVersion(SPI_Typedef* SPIx);
void SPI_SystemInterruptEnable(SPI_Typedef* SPIx);
void SPI_SystemInterruptDisable(SPI_Typedef* SPIx);
int  SPI_GetIndex(SPI_Typedef* SPIx);
void SPI_Cleanup(SPI_Typedef* SPIx);

#endif /* __ACH118X_SSI_H */

/************************ (C) COPYRIGHT ART *****END OF FILE****/
