/*********************************************************************************************************                                               
*                                     MCU ACH118X driver library
*                             COPYRIGHT(c) 2019 Amped RF Technology (ART)
*                                        All Rights Reserved
*
* File		: ach118x_i2c.h
* Version	: V1.0.0
* Brief		: I2C Definitions
*  - Data structures and the address mapping for I2C
*  - Macros and prototypes to access I2C hardware
**********************************************************************************************************/

#ifndef __ACH118X_I2C_H
#define __ACH118X_I2C_H

/*I2C register define*/
typedef struct
{
	vu32 CON;               //0x0,I2C Control Register
	vu32 TAR;               //0x4,I2C Target Address Register
	vu32 SAR;               //0x8,I2C Slave Address Register
	vu32 HS_MADDR;          //0xc,I2C High Speed Master Mode Code Address Register
	vu32 DATA_CMD;          //0x10,I2C Rx/Tx Data Buffer and Command Register
	vu32 SS_SCL_HCNT;       //0x14,Standard Speed I2C Clock SCL High Count Register
	vu32 SS_SCL_LCNT;       //0x18,Standard Speed I2C Clock SCL Low Count Register
	vu32 FS_SCL_HCNT;       //0x1c, Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
	vu32 FS_SCL_LCNT;       //0x20,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
	vu32 HS_SCL_HCNT;       //0x24,High Speed I2C Clock SCL High Count Register
	vu32 HS_SCL_LCNT;       //0x28,High Speed I2C Clock SCL Low Count Register
	vu32 INTR_STAT;         //0x2c,I2C Interrupt Status Register
	vu32 INTR_MASK;         //0x30, I2C Interrupt Mask Register
	vu32 RAW_INTR_STAT;     //0x34,I2C Raw Interrupt Status Register
	vu32 RX_TL;             //0x38,I2C Receive FIFO Threshold Register
	vu32 TX_TL;             //0x3c,I2C Transmit FIFO Threshold Registe
	vu32 CLR_INTR;          //0x40,Clear Combined and Individual Interrupt Register
	vu32 CLR_RX_UNDER;	    //0x44,Clear RX_UNDER Interrupt Register
	vu32 CLR_RX_OVER;       //0x48,Clear RX_OVER Interrupt Register
	vu32 CLR_TX_OVER;       //0x4c,Clear TX_OVER Interrupt Register
	vu32 CLR_RD_REQ;        //0x50,Clear RD_REQ Interrupt Register
	vu32 CLR_TX_ABRT;       //0x54,Clear TX_ABRT Interrupt Register
	vu32 CLR_RX_DONE;       //0x58,Clear RX_DONE Interrupt Register
	vu32 CLR_ACTIVITY;      //0x5c,Clear ACTIVITY Interrupt Register
	vu32 CLR_STOP_DET;      //0x60,Clear STOP_DET Interrupt Register
	vu32 CLR_START_DET;     //0x64,Clear START_DET Interrupt Register
	vu32 CLR_GEN_CALL;      //0x68,Clear GEN_CALL Interrupt Register
	vu32 ENABLE;            //0x6c, I2C Enable Register
	vu32 STATUS;            //0x70, I2C Status Register
	vu32 TXFLR;             //0x74, I2C Transmit FIFO Level Register
	vu32 RXFLR;             //0x78,I2C Receive FIFO Level Register
	vu32 SDA_HOLD;		    //0x7c,I2C SDA Hold Time Length Register
	vu32 TX_ABRT_SOURCE;    //0x80, I2C Transmit Abort Source Register
	vu32 SLV_DATA_NACK_ONLY;//0x84,Generate Slave Data NACK Register
	vu32 DMA_CR;            //0x88,DMA Control Register
	vu32 DMA_TDLR;		    //0x8c,DMA Transmit Data Level Register
	vu32 DMA_RDLR;		    //0x90,I2C Receive Data Level Register
	vu32 SDA_SETUP;         //0x94,I2C SDA Setup Register
	vu32 ACK_GENERAL_CALL;  //0x98,I2C ACK General Call Register
	vu32 ENABLE_STATUS;     //0x9c,I2C Enable Status Register
	vu32 FS_SPKLEN;		    //0xA0,I2C SS and FS Spike Suppression Limit Register
	vu32 HS_SPKLEN;         //0xA4,I2C HS Spike Suppression Limit Register
	vu32 CLR_RESTART_DET;   //0xA8,Clear RESTART_DET Interrupt Register
	vu32 ReseverAC;         //

	vu32 ReseverB0;//
	vu32 ReseverB4;//
	vu32 ReseverB8;//
	vu32 ReseverBC;//

	vu32 ReseverC0;//
	vu32 ReseverC4;//
	vu32 ReseverC8;//
	vu32 ReseverCC;//

	vu32 ReseverD0;//
	vu32 ReseverD4;//
	vu32 ReseverD8;//
	vu32 ReseverDC;//

	vu32 ReseverE0;//
	vu32 ReseverE4;//
	vu32 ReseverE8;//
	vu32 ReseverEC;//

	vu32 ReseverF0;//
	vu32 COMP_PARAM_1;      //0xf4,Clear RESTART_DET Interrupt Register
	vu32 COMP_VERSION;      //0xf8,I2C Component Version Register
	vu32 COMP_TYPE;		    //0xfc, I2C Component Type Register
}I2C_Typedef;

typedef enum {I2C_MASTER = 0, I2C_SLAVE = !I2C_MASTER} RoleType;
#define I2C_MASTER_MASK(X)	        ((X) |= (0x41))
#define I2C_SLAVE_MASK(X)		((X) &= (0xBE))

typedef enum {I2C_ADDR_7BIT = 0, I2C_ADDR_10BIT = !I2C_ADDR_7BIT} AddrType;
#define I2C_ADDR_7BIT_MASK(X)	        ((X) &= (0xE7))
#define I2C_ADDR_10BIT_MASK(X)		((X) |= (0x18))

typedef enum {
    I2C_DutyCycle_1_4 = 0,
    I2C_DutyCycle_1_2 = 1,
    I2C_DutyCycle_3_4 = 3
} DutyCycleType;

#define I2C_STANDARD_MODE_MASK(X)	(X) &= (0xFB);(X) |= (0x02)
#define I2C_FAST_MODE_MASK(X)	        (X) |= (0x04);(X) &= (0xFD)
#define I2C_HIGH_MODE_MASK(X)		((X) |= (0x06))
#define I2C_RESTART_EN_MASK(X)	        ((X) |= (0x20))

typedef struct
{
    RoleType I2C_Role;
    AddrType I2C_AddrType;
    uint32_t I2C_ClockSpeed;
    DutyCycleType I2C_DutyCycle;
    uint16_t I2C_AckAddress;
    uint16_t I2C_OwnAddress;
    FunctionalState I2C_Ack;
}I2C_InitTypeDef;

//IC_CLR_INTR
#define INTR                            (0x0000)
//IC_RAW_INTR_STAT
#define RX_UNDER                        (0x0001)
#define RX_OVER                         (0x0002)
#define RX_FULL                         (0x0004)
#define TX_OVER                         (0x0008)
#define TX_EMPTY                        (0x0010)
#define RD_REQ                          (0x0020)
#define TX_ABRT                         (0x0040)
#define RX_DONE                         (0x0080)
#define ACTIVITY                        (0x0100)
#define STOP_DET                        (0x0200)
#define START_DET                       (0x0400)
#define GEN_CALL                        (0x0800)
#define RESTART_DET                     (0x1000)
#define MST_ON_HOLD                     (0x2000)
//CLR_RESTART_DET
//#define RESTART_DET                     (0xFFFF)

//IC_STATUS  ( I2C Status Register)
#define SLV_HOLD_RX_FIFO_FULL           (0x400)
#define SLV_HOLD_TX_FIFO_EMPT           (0x200)
#define MST_HOLD_RX_FIFO_FULL           (0x100)
#define MST_HOLD_TX_FIFO_EMPTY          (0x080)
#define SLV_ACTIVITY                    (0x040)
#define MST_ACTIVITY                    (0x020)
#define REC_FIFO_FULL                   (0x010)
#define REC_FIFP_NOT_EMPTY              (0x008)
#define TRA_FIFO_EMPTY                  (0x004)
#define TRA_FIFO_NOT_FULL               (0x002)
#define ACTIVITY_STATUS                 (0x001)

//IC_COMP_PARAM_1
    //BIT[1:0]
#define I2C_APB_DATA_WIDTH_8BIT         (0x00)
#define I2C_APB_DATA_WIDTH_16BIT        (0x01)
#define I2C_APB_DATA_WIDTH_32BIT        (0x02)
    //BIT[3:2]
#define MAX_SPEED_MODE_STANDARD         (0x01<<2)
#define MAX_SPEED_MODE_FAST             (0x02<<2)
#define MAX_SPEED_MODE_HIGH             (0x03<<2)

#define HC_COUNT_VALUES                 (0x1<<4)
#define INTR_IO                         (0x1<<5)
#define HAS_DMA                         (0x1<<6)
#define ADD_ENCODED_PARAM               (0x1<<7)

// prototypes
void I2C_Init(I2C_Typedef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_SendData(I2C_Typedef* I2Cx, uint8_t Data);
unsigned char GKI_I2CReceiveData(I2C_Typedef* I2Cx);
unsigned char I2C_ReceiveData(I2C_Typedef* I2Cx);

#endif // __ACH118X_I2C_H
/************************ (C) COPYRIGHT ART *****END OF FILE****/
