/*********************************************************************************************************                                               
*                                     MCU ACH118X driver library
*                             COPYRIGHT(c) 2019 Amped RF Technology (ART)
*                                        All Rights Reserved
*
* File    : ach118x_dma.h
* Version : V1.0.0
* Brief   :
*  - Data structures and the address mapping for DMA
*  - DMA registers declarations and bits definition
*  - Macros to access DMA register hardware
*
**********************************************************************************************************/

#ifndef __ACH118X_DMA_H
#define __ACH118X_DMA_H

/**********************************************/
/*         DMA Register Memory Map            */
/*         Do Not USE DMA in MPW ACH versions */
/**********************************************/

typedef struct {
    vu64
        INT_EN              : 1,    // Interrupt Enable
        DST_TR_WIDTH        : 3,    // Destination Transfer Width
        SRC_TR_WIDTH        : 3,    // Source Transfer Width
        DINC                : 2,    // Destination Address Increment
        SINC                : 2,    // Source Address Increment
        DEST_MSIZE          : 3,    // Destination Burst Transaction Length
        SRC_MSIZE           : 3,    // Source Burst Transaction Length
        SRC_GATHER_EN       : 1,    // Source gather enable
        DST_SCATTER_EN      : 1,    // Destination scatter enable
        Undefined_19        : 1,
        TT_FC               : 2,    // Transfer Type and Flow Control
        DMS                 : 2,    // Destination Master Select
        SMS                 : 2,    // Source Master Select
        LLP_DST_EN          : 1,    // Block chaining is enabled on dest
        LLP_SRC_EN          : 1,    // Block chaining is enabled on src
        Undefined_31_29     : 3,
        BLOCK_TS            : 12,   // Block Transfer Size
        DONE                : 1,    // Done bit
        Undefined_63_45     : 19;
} DMA_CTL_Typedef;

typedef struct {
    vu64
        Undefined_4_0       : 5,
        CH_PRIOR            : 3,    // Channel priority
        CH_SUSP             : 1,    // Channel Suspend
        FIFO_EMPTY          : 1,    // Indicates no data in FIFO
        HS_SEL_DST          : 1,    // Dst Software or Hardware Handshaking Select
        HS_SEL_SRC          : 1,    // Src Software or Hardware Handshaking Select
        LOCK_CH_L           : 2,    // Channel Lock Level
        LOCK_B_L            : 2,    // Bus Lock Level
        LOCK_CH             : 1,    // Channel Lock Bit
        LOCK_B              : 1,    // Bus Lock Bit
        DST_HS_POL          : 1,    // Destination Handshaking Interface Polarity
        SRC_HS_POL          : 1,    // Source Handshaking Interface Polarity
        MAX_ABRST           : 10,   // Maximum AMBA Burst Length
        RELOAD_SRC          : 1,    // Automatic Source Reload
        RELOAD_DST          : 1,    // Automatic Destination Reload
        FCMODE              : 1,    // Flow Control Mode
        FIFO_MODE           : 1,    // FIFO Mode Select
        PROTCTL             : 3,    // Protection Control
        DS_UPD_EN           : 1,    // Destination Status Update Enable
        SS_UPD_EN           : 1,    // Source Status Update Enable
        SRC_PER             : 4,    // 42:39 hardware handshaking interface
        DEST_PER            : 4,    // 46:43 hardware handshaking interface
        Undefined_63_47     : 17;
} DMA_CFG_Typedef;

typedef struct
{
    vu64 SAR;               // 0x000 R/W  Source Address Register
    vu64 DAR;               // 0x008 R/W  Destination Address Register
    vu64 LLP;               // 0x010 R/W  Linked List Pointer Register
    DMA_CTL_Typedef CTL;    // 0x018 R/W  Control Register
    vu64 SSTAT;             // 0x020 R/W  Source Status Register
    vu64 DSTAT;             // 0x028 R/W  Destination Status Register
    vu64 SSTATAR;           // 0x030 R/W  Source Status Address Register
    vu64 DSTATAR;           // 0x038 R/W  Destination Status Address Register
    DMA_CFG_Typedef CFG;    // 0x040 R/W  Configuration Register
    vu64 SGR;               // 0x048 R/W  Source Gather Register
    vu64 DSR;               // 0x050 R/W  Destination Scatter Register
} DMA_Channel_Typedef;

typedef struct
{
    DMA_Channel_Typedef Ch[8]; // DMA Channels 0-7
    vu64 RawTfr;            // 0x2C0 R    Raw Status for IntTfr Interrupt
    vu64 RawBlock;          // 0x2C8 R    Raw Status for IntBlock Interrupt
    vu64 RawSrcTran;        // 0x2D0 R    Raw Status for IntSrcTran Interrupt
    vu64 RawDstTran;        // 0x2D8 R    Raw Status for IntDstTran Interrupt
    vu64 RawErr;            // 0x2E0 R    Raw Status for IntErr Interrupt
    vu64 StatusTfr;         // 0x2E8 R    Status for IntTfr Interrupt
    vu64 StatusBlock;       // 0x2F0 R    Status for IntBlock Interrupt
    vu64 StatusSrcTran;     // 0x2F8 R    Status for IntSrcTran Interrupt
    vu64 StatusDstTran;     // 0x300 R    Status for IntDstTran Interrupt
    vu64 StatusErr;         // 0x308 R    Status for IntErr Interrupt
    vu64 MaskTfr;           // 0x310 R/W  Mask for IntTfr Interrupt
    vu64 MaskBlock;         // 0x318 R/W  Mask for IntBlock Interrupt
    vu64 MaskSrcTran;       // 0x320 R/W  Mask for IntSrcTran Interrupt
    vu64 MaskDstTran;       // 0x328 R/W  Mask for IntDstTran Interrupt
    vu64 MaskErr;           // 0x330 R/W  Mask for IntErr Interrupt
    vu64 ClearTfr;          // 0x338 W    Clear for IntTfr Interrupt
    vu64 ClearBlock;        // 0x340 W    Clear for IntBlock Interrupt
    vu64 ClearSrcTran;      // 0x348 W    Clear for IntSrcTran Interrupt
    vu64 ClearDstTran;      // 0x350 W    Clear for IntDstTran Interrupt
    vu64 ClearErr;          // 0x358 W    Clear for IntErr Interrupt
    vu64 StatusInt;         // 0x360 W    Status for each interrupt type
    vu64 ReqSrcReg;         // 0x368 R/W  Source Software Transaction Request Register
    vu64 ReqDstReg;         // 0x370 R/W  Destination Software Transaction Request Register
    vu64 SglReqSrcReg;      // 0x378 R/W  Single Source Transaction Request Register
    vu64 SglReqDstReg;      // 0x380 R/W  Single Destination Transaction Request Register
    vu64 LstSrcReg;         // 0x388 R/W  Last Source Transaction Request Register
    vu64 LstDstReg;         // 0x390 R/W  Last Destination Transaction Request Register
    vu64 DmaCfgReg;         // 0x398 R/W  DMA Configuration Register
    vu64 ChEnReg;           // 0x3A0 R/W  DMA Channel Enable Register
    vu64 DmaIdReg;          // 0x3A8 R    DMA ID Register
    vu64 DmaTestReg;        // 0x3B0 R/W  DMA Test Register
    vu64 Reserved_3B8;      //
    vu64 Reserved_3C0;      //
    vu64 DMA_COMP_PARAMS_6; // 0x3C8 R
    vu64 DMA_COMP_PARAMS_5; // 0x3D0 R
    vu64 DMA_COMP_PARAMS_4; // 0x3D8 R
    vu64 DMA_COMP_PARAMS_3; // 0x3E0 R
    vu64 DMA_COMP_PARAMS_2; // 0x3E8 R
    vu64 DMA_COMP_PARAMS_1; // 0x3F0 R
    vu64 DMA_ComponentID;   // 0x3F8 R   Component version register.
} DMA_Typedef;


// DmaCfgReg
#define DMA_EN  0x01

// DmaEnReg
#define DMA_CH0_EN      0x0001
#define DMA_CH1_EN      0x0002
#define DMA_CH2_EN      0x0004
#define DMA_CH3_EN      0x0008
#define DMA_CH4_EN      0x0010
#define DMA_CH5_EN      0x0020
#define DMA_CH6_EN      0x0040
#define DMA_CH7_EN      0x0080
#define DMA_CH0_EN_WE   0x0100
#define DMA_CH1_EN_WE   0x0200
#define DMA_CH2_EN_WE   0x0400
#define DMA_CH3_EN_WE   0x0800
#define DMA_CH4_EN_WE   0x1000
#define DMA_CH5_EN_WE   0x2000
#define DMA_CH6_EN_WE   0x4000
#define DMA_CH7_EN_WE   0x8000

// DMA CTL
#define DMA_Increment   0
#define DMA_Decrement   1
#define DMA_Fixed       2

#define DMA_MSIZE_1     0
#define DMA_MSIZE_4     1
#define DMA_MSIZE_8     2
#define DMA_MSIZE_16    3
#define DMA_MSIZE_32    4
#define DMA_MSIZE_64    5
#define DMA_MSIZE_128   6
#define DMA_MSIZE_256   7

#define DMA_WIDTH_8     0
#define DMA_WIDTH_16    1
#define DMA_WIDTH_32    2
#define DMA_WIDTH_64    3
#define DMA_WIDTH_128   4
#define DMA_WIDTH_256   5

#define DMA_DIR_MemoryToMemory          0
#define DMA_DIR_MemoryToPeripheral      1
#define DMA_DIR_PeripheralToMemory      2
#define DMA_DIR_PeripheralToPeripheral  3



//prototypes
uint32_t DMA_GetComponentID(void);


#endif /* __ACH118X_DMA_H */
/************************ (C) COPYRIGHT ART *****END OF FILE****/
