/*********************************************************************************************************                                               
*                                     MCU ACH118X driver library
*                             COPYRIGHT(c) 2019 Amped RF Technology (ART)
*                                        All Rights Reserved
*
* File    : ach118x_tim.h
* Version : V1.0.0
* Brief   : add here, if there is some important to say.
*  - Data structures and the address mapping for TIM
*  - TIM registers declarations and bits definition
*  - Macros to access TIM register hardware
**********************************************************************************************************/

#ifndef __ACH118X_TIM_H
#define __ACH118X_TIM_H

/*************************************************************************/
/*                   TIMER Definitions                                   */
/*************************************************************************/
#define TIM0_REG_BASE           (TIM_REG_BASE | 0x00)
#define TIM1_REG_BASE           (TIM_REG_BASE | 0x14)
#define TIM2_REG_BASE           (TIM_REG_BASE | 0x28)
#define TIM3_REG_BASE           (TIM_REG_BASE | 0x3C)
#define TIM4_REG_BASE           (TIM_REG_BASE | 0x50)
#define TIM5_REG_BASE           (TIM_REG_BASE | 0x64)
#define TIM6_REG_BASE           (TIM_REG_BASE | 0x78)
#define TIM7_REG_BASE           (TIM_REG_BASE | 0x8C)

#define TIM_LOAD_COUNT      0x00
#define TIM_CURRENT_VALUE   0x04
#define TIM_CTRL_REG        0x08
#define TIM_EOI             0x0C
#define TIM_INT_STATUS      0x10


#define TimersIntStatus         *(uint8_t *)(TIM_REG_BASE | 0xA0)   // TimerN Control Register
#define TimersEOI               *(uint8_t *)(TIM_REG_BASE | 0xA4)   // TimerN End-of-Interrupt Register
#define TimersRawIntStatus      *(uint8_t *)(TIM_REG_BASE | 0xA8)
#define TIMERS_COMP_VERSION     *(uint8_t *)(TIM_REG_BASE | 0xAC)

// TIM 1-8
typedef struct {
    __IO uint32_t   LoadCount;      // TimerN Load Count Register (32 bits)
    __IO uint32_t   CurrentValue;   // TimerN Current Value Register (32 bits)
    __IO uint32_t   ControlReg;     // TimerN Control Register (3 bits)
    __IO uint32_t   EOI;            // TimerN End-of-Interrupt Register (1 bit)
    __IO uint32_t   IntStatus;      // TimerN Interrupt Status Register (1 bit)
} TIMER_REG_Typedef;


#define TIM0    ((TIMER_REG_Typedef *) TIM0_REG_BASE)
#define TIM1    ((TIMER_REG_Typedef *) TIM1_REG_BASE)
#define TIM2    ((TIMER_REG_Typedef *) TIM2_REG_BASE)
#define TIM3    ((TIMER_REG_Typedef *) TIM3_REG_BASE)
#define TIM4    ((TIMER_REG_Typedef *) TIM4_REG_BASE)
#define TIM5    ((TIMER_REG_Typedef *) TIM5_REG_BASE)
#define TIM6    ((TIMER_REG_Typedef *) TIM6_REG_BASE)
#define TIM7    ((TIMER_REG_Typedef *) TIM7_REG_BASE)


//TimerNControlReg
#define TIM_CTRL_ENABLE     0x01
#define TIM_CTRL_LOAD_COUNT 0x02
#define TIM_CTRL_INT_MASK   0x04

// prototypes
uint32_t tim_GetCounter(TIMER_REG_Typedef* TIMx);


#endif /* __ACH118X_TIM_H */
/************************ (C) COPYRIGHT ART *****END OF FILE****/
